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8M x 36-Bit EDO - DRAM Module
HYM 368025S/GS-50/-60
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SIMM modules with 8 388 608 words by 36-bit organization in two banks for PC main memory applications Fast access and cycle time 50 ns access time 84 ns cycle time (-50 version) 60 ns access time 104 ns cycle time (-60 version) Hyper Page Mode (EDO) capability 20 ns cycle time (-50 version) 25 ns cycle time (-60 version) Single + 5 V ( 10 %) supply Low power dissipation max. 6820 mW active (-50 version) max. 6160 mW active (-60 version) CMOS - 132 mW standby TTL -264 mW standby CAS-before-RAS refresh RAS-only-refresh Hidden-refresh Decoupling capacitors mounted on substrate All inputs, outputs and clocks fully TTL compatible 72 pin Single in-Line Memory Module (L-SIM-72-14) with 31.75 mm height Utilizes sixteen 4Mx4-EDO-DRAMs and eight 4M x 1 EDO-DRAMs in 300 mil wide SOJ packages 2048 refresh cycles / 32 ms Optimized for use in byte-write parity applications Tin-Lead contact pads (S- version) Gold contact pads (GS - version)
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Semiconductor Group
1
4.97
HYM 368025S/GS-50/-60 8M x 36-Bit EDO-Module
The HYM 368025S/GS-50/-60 is a 32 MByte DRAM module organized as 8 388 608 words by 36Bit in two banks in a 72-pin single-in-line package comprising sixteen HYB 5117405BJ 4M x 4 EDO-DRAMs and eight HYB 514105BJ 4M x 1 EDO-DRAMs in 300 mil wide SOJ-packages mounted together with decoupling capacitors on a PC board. Each HYB 5117405BJ and HYB 514105BJ is described in the data sheet and is fully electrical tested and processed according to SIEMENS standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The speed of the module can be detected by the use of four presence detect pins. The common I/O feature on the HYM 368025S/GS-50/-60 dictates the use of early write cycles. Ordering Information Type HYM 368025S-50 HYM 368025S-60 HYM 368025GS-50 HYM 368025GS-60 Ordering Code Package L-SIM-72-14 L-SIM-72-14 L-SIM-72-14 L-SIM-72-14 Description EDO-DRAM Module (access time 50 ns) EDO-DRAM Module (access time 60 ns) EDO-DRAM Module (access time 50 ns) EDO-DRAM Module (access time 60 ns)
Semiconductor Group
2
HYM 368025S/GS-50/-60 8M x 36-Bit EDO-Module
Pin Configuration
Pin Names
VSS 1 DQ0 2 DQ18 3 DQ1 4 DQ19 5 DQ2 6 DQ20 7 DQ3 8 DQ21 9 VCC 10 N.C. 11 A0 12 A1 13 A2 14 A3 15 A4 16 A5 17 A6 18 A10 19 DQ4 20 DQ22 21 DQ5 22 DQ23 23 DQ6 24 DQ24 25 DQ7 26 DQ25 27 A7 28 N.C. 29 VCC 30 A8 31 A9 32 RAS3 33 RAS2 34 DQ26 35 DQ8 36 DQ17 37 DQ35 38 VSS 39 CAS0 40 CAS2 41 CAS3 42 CAS1 43 RAS0 44 RAS1 45 N.C. 46 WE 47 N.C. 48 DQ9 49 DQ27 50 DQ10 51 DQ28 52 DQ11 53 DQ29 54 DQ12 55 DQ30 56 DQ13 57 DQ31 58 VCC 59 DQ32 60 DQ14 61 DQ33 62 DQ15 63 DQ34 64 DQ16 65 N.C. 66 PD0 67 PD1 68 PD2 69 PD3 70 N.C. 71 VSS 72
A0-A10 DQ0-DQ35 CAS0 - CAS3 RAS0- RAS3 WE
Address Inputs Data Input/Output Column Address Strobe Row Address Strobe Read/Write Input Power (+ 5 V) Ground Presence Detect Pin No Connection
VCC VSS
PD N.C.
Presence Detect Pins -50 PD0 PD1 PD2 PD3 N.C. -60 N.C.
VSS VSS VSS
VSS
N.C. N.C.
Semiconductor Group
3
HYM 368025S/GS-50/-60 8M x 36-Bit EDO-Module
RAS0 CAS0 DQ0-DQ3 CAS RAS I/O1-I/O4 OE D0 CAS RAS I/O1-I/O4 OE D3 Di Do CAS RAS M0
RAS1
CAS RAS I/O1-I/O4 OE D1 CAS RAS I/O1-I/O4 D2 OE Di Do CAS RAS M1
DQ4-DQ7 DQ8 CAS1 DQ9-DQ12
CAS RAS I/O1-I/O4 OE D4 CAS RAS I/O1-I/O4 OE D7 Di Do CAS RAS M2 RAS3
CAS RAS I/O1-I/O4 OE D5 CAS RAS I/O1-I/O4 D6 OE Di Do CAS RAS M3
DQ13-DQ16 DQ17 RAS2 CAS2
DQ18-DQ21 DQ22-DQ25 DQ26 CAS3
CAS RAS I/O1-I/O4 OE D8 CAS RAS I/O1-I/O4 OE D11 Di Do CAS RAS M4
CAS RAS I/O1-I/O4 OE D9 CAS RAS I/O1-I/O4 D10 OE Di Do CAS RAS M5
DQ27-DQ30 DQ31-DQ34
CAS RAS I/O1-I/O4 OE D12 CAS RAS I/O1-I/O4 D15 OE Di Do CAS RAS M6 VCC VSS
CAS RAS I/O1-I/O4 OE D13 CAS RAS I/O1-I/O4 D14 OE Di Do CAS RAS M7
DQ35
A0-A10 WE
D0-D15, M0-M7 D0-D15, M0-M7
C0 - C23
Block Diagram
Semiconductor Group
4
HYM 368025S/GS-50/-60 8M x 36-Bit EDO-Module
Absolute Maximum Ratings Operation temperature range ......................................................................................... 0 to + 70 C Storage temperature range......................................................................................... - 55 to 125 C Input/output voltage ............................................................................ -0.5V to min (Vcc+0.5, 7.0) V Power supply voltage...................................................................................................... - 1 to + 7 V Power dissipation................................................................................................................... 9.24 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics TA = 0 to 70 C, VCC = 5 V 10 % Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current (0 V < VIN < 6.5 V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V < VOUT < 5.5 V) Average VCC supply current (RAS, CAS, address cycling, tRC = tRC min) -50 version -60 version Standby VCC supply current (RAS = CAS = VIH) Average VCC supply current during RAS only refresh cycles (per bank) (RAS cycling, CAS = VIH, tRC = tRC min) -50 version -60 version Symbol Limit Values min. max. Vcc+0.5 0.8 - 0.4 20 20 V V V V A A 2.4 - 0.5 2.4 - - 20 - 20 Unit Test Condition
1) 1) 1) 1) 1)
VIH VIL VOH VOL II(L) IO(L) ICC1
1)
- -
1240 1120 48
mA mA mA
2),3),4)
ICC2 ICC3
-
- -
1240 1120
mA mA
2),4)
Semiconductor Group
5
HYM 368025S/GS-50/-60 8M x 36-Bit EDO-Module
DC Characteristics1) (cont' d) Parameter Average VCC supply current during fast page mode (RAS = VIL, CAS, address cycling, tPC = tPC min) -50 version -60 version Standby VCC supply current (RAS = CAS = VCC - 0.2 V) Average VCC supply current during CASbefore-RAS refresh mode (per bank) (RAS, CAS cycling, tRC = tRC min) -50 version -60 version Symbol Limit Values min. max. Unit Test Condition
ICC4
- -
840 680 24
mA mA mA
2),3),4)
ICC5 ICC6
-
- -
1240 1120
mA mA
2),4)
Capacitance TA = 0 to 70 C, VCC = 5 V 10 %, f = 1 MHz Parameter Input capacitance (A0 to A10,WE) Input capacitance (RAS0 - RAS3) Input capacitance (CAS0 - CAS3) I/O capacitance (DQ0-DQ35) Symbol Limit Values min. max. 180 50 40 25 pF pF pF pF - - - - Unit
CI1 CI2 CI3 CIO
Semiconductor Group
6
HYM 368025S/GS-50/-60 8M x 36-Bit EDO-Module
AC Characteristics 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 2 ns Parameter
Symbol
Limit Values -50 min. max. min. -60 max.
Unit
Note
common parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF 84 30 50 8 0 8 0 8 12 10 13 40 5 1 - - 50 32 - - 10k 10k - - - - 37 25 104 40 60 10 0 10 0 10 14 12 15 50 5 1 - - - 10k 10k - - - - 45 30 - - - 50 32 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7
Read Cycle
Access time from RAS Access time from CAS Access time from column address Column address to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay tRAC tCAC tAA tRAL tRCS tRCH tRRH tCLZ tOFF - - - 25 0 0 0 0 0 50 13 25 - - - - - 13 - - - 30 0 0 0 0 0 60 15 30 - - - - - 15 ns ns ns ns ns ns ns ns ns 11 11 8 12 8, 9 8, 9 8,10
Semiconductor Group
7
HYM 368025S/GS-50/-60 8M x 36-Bit EDO-Module
AC Characteristics (cont' d) 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 2 ns Parameter
Symbol
Limit Values -50 min. max. min. -60 max.
Unit
Note
Early Write Cycle
Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time tWCH tWP tWCS tRWL tCWL tDS tDH 8 8 0 13 13 0 8 - - - - - - - 10 10 0 15 15 0 10 - - - - - - - ns ns ns ns ns ns ns 14 14 13
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time CAS precharge time Access time from CAS precharge Output data hold time RAS pulse width in hyper page mode CAS precharge to RAS Delay tHPC tCP tCPA tCOH tRAS tRHCP 20 8 - 5 50 27 - - 27 - 200k - 25 10 - 5 60 32 - - 32 - 200k - ns ns ns ns ns ns 7
CAS before RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS tCSR tCHR tRPC tWRP tWRH 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - ns ns ns ns ns
Semiconductor Group
8
HYM 368025S/GS-50/-60 8M x 36-Bit EDO-Module
Notes:
1) All voltages are referenced to VSS. Vil may undershoot to -2.0 V for pulse width of less than or equal to 4 ns. Pulse width is measured at 50% points with amplitude measured peak to the DC reference. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle. 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume
tT = 2 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined by the latter of t RAC, tCAC, tAA,tCPA . tCAC is measured from tristate. . 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13) tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.) , the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle. 14) These parameters are referenced to the CAS leading edge.
Semiconductor Group
9
HYM 368025S/GS-50/-60 8M x 36-Bit EDO-Module
Package Outline
Dimensions in mm
GLS05858
Module Package, L-SIM-72-14 (Single in-Line Memory Module)
Semiconductor Group
10

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